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| MSP430F2001IPWR资料 | |
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MSP430F2001IPWR PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:The enhanced configuration device flash memories feature a 90-ns access time (approximately 10 MHz). Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[], at 10 MHz). However, the configuration speeds supported by Altera FPGAs are much higher and translate to high configuration write bandwidths. For instance, 100-MHz Stratix FPP configuration requires data at the rate of 800 Mbps (8-bit DATA[] bus at 100 MHz). This is much higher than the 160 Mbps the flash memory can support, and is the limiting factor for configuration time. Compression increases the effective flash read bandwidth since the same amount of configuration data takes up less space in the flash memory after compression. Since Stratix configuration data compression ratios are approximately two, the effective read bandwidth doubles to about 320 Mbps. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：MSP430F2001IPWR 厂 家：TI 封 装：TSSOP 批 号：18+ 数 量：5000 说 明： 只做全新进口原装，现货热卖，欢迎采购，联系人：张先生 /余小姐 电话：021-61316867 / 18916952726 |
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运 费： 所在地： 新旧程度：全新 |
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